Hsinchu City Taiwan
- Blocks design, SoC design and integration
- Design simulation and verification
- Run all digital design flow(synthesis/STA/lint/LEC/…)
- FPGA build up and verification
- BS, MS or PhD in electrical engineering, computer engineering or computer science with a special focus on digital system design, computer architecture or computer hardware design.
- 0~10 years of industry experience
- Experience in RTL design(design many modules from scratch). Verilog is required and SystemVerilog is a must.
- Experience in ARM processor, bus design, SoC integration, standard interfaces protocols and common IP blocks.
- Experience in design flows for simulation, synthesis, verification, design for testing, static timing analysis, logic equivalence check, etc.
- Experience in chip tape-out and volume production, especially in sub-40nm nodes.
- Skilled in system verification such as FPGA prototype buildup and debug.
- Familiarity with script programming such as shell script, make, Python, etc.
- Willing to take on challenges, and effective English communications and co-work with other team members.
Compensation and benefits
- Salary + bonus: NTD 1M-3M/year according to experience
- Stock option offerings
- Generous PTO and benefits
- High growth potential